1. Field of the Invention
This invention relates to circuits for interfacing centralized control circuits with a plurality of peripheral circuits and in particular to those interface circuits which contain error check circuitry for detecting internal circuit faults.
2. Description of the Prior Art
In many real time systems, it is necessary that a number of peripheral circuits operate under control of a centralized control circuit which is often a stored program processing unit. One method of controlling the peripheral circuits is to connect each peripheral circuit directly to the central control. When the number of peripheral circuits becomes large, a direct connection scheme is often impractical and it becomes necessary to perform time division multiplexing on the outgoing command signals and incoming data in order to efficiently use the capabilities of the central control.
The job of multiplexing incoming data and decoding outgoing control circuits may be performed by an interfacing read and write circuit. The central control provides the interface circuit with an address which uniquely identifies one of the peripheral circuits. If the control circuit wishes to perform some operation on a peripheral circuit, a data command is also forwarded to the interface circuit. The interface circuit utilizes the address and data provided to develop a signal which is then forwarded to the identified peripheral unit. Similarly, if the central control desires to interrogate a peripheral unit to determine its state, it provides an address code and a read command to the interface circuit which then causes the identified peripheral unit to be temporarily connected to the central control information bus. Interface units such as that described above are well known in the computer and telecommunications switching art.
However, when an interface unit is placed between control and peripheral circuits, the system reliability is reduced since the interface unit is itself subject to internal circuit failures. In order to increase reliability, it has become standard practice to perform maintenance operations on the interface unit to detect internal failures.
In the prior art, in order to perform a maintenance check, for example, on the readout multiplexor which reads the states of the peripheral units and forwards them to the control circuit, the inputs to the mulitplexor were disconnected from the peripheral units and connected to a source of data whose states were known. The multiplexor then was cycled through all of its states and the output was compared to the known data input to detect internal failures. This method of checking for circuit failures was effective in that all internal circuitry of the multiplexor could be checked. However, it required the normal operation of the circuit to be halted while the maintenance operation was being performed. It is thus desirable to have a read and write circuit which can perform a maintenance check for internal circuit failures while the circuit is in operation.
Accordingly, it is an object of the present invention to provide a self-checking read and write circuit which automatically performs maintenance checks for internal circuit failures without halting the operation of the circuit.
It is a further object of the present invention to provide a read and write circuit with a self-checking feature which does not require extensive circuitry for the maintenance operation.